1. Field of the Invention
The invention relates generally to apparatus for producing clock drive signals and in particular to apparatus for selectively producing one clock drive frequency from a plurality of frequencies for driving logical components with different timing requirements but within a common computer system.
2. Description of the Prior Art
Modern data processing systems include a plurality of subsystems and/or a plurality of different types and generations of peripheral devices. The operation of the subsystems and the peripherals is often asynchronous with respect to a central processing unit (CPU). Typically, a cluster of peripheral devices are controlled and driven by a common control unit which may be connected directly to the CPU or may be more likely connected indirectly to the CPU by means of a peripheral control unit (PCU). In either event, the control unit operates asynchronously from a CPU (and/or the PCU).
Despite the general asynchronous operation of the control unit and its associated peripheral devices, the CPU nonetheless imposes system timing requirements on the operation of the control unit in the driving of the peripherals. Consequently, drive clocks for driving peripheral units (typically contained within the control unit) have to be built to satisfy two divergent, though non-conflicting, sets of parameters. First, the drive frequency for controlling the operation of a specific peripheral unit has to be the frequency which matches the timing requirements of the peripheral unit. Secondly, the initialization and termination of the drive frequency has to be coordinated with the master system clock so as to properly communicate with other system apparati.
Typical prior art solutions to this problem involved building a drive clock on a printed circuit board, and including the drive clock in a magnetic tape controller (MTC). The MTC was then coupled to a plurality of tape drives with identical drive frequency requirements. Control of the single-frequency clock drive was coordinated with the master system clock to assure satisfaction of the system timing requirements.
The problem was complicated, however, by the evolution of new peripheral units with slightly different drive frequency requirements from older versions of similar components. (An example is the evolution of tape drives). Prior art solutions to this problem required attaching only peripheral devices with identical timing requirements to any single-frequency control unit. This required building different control units capable of emitting different drive frequencies for each set of peripheral devices with different timing requirements. However, it is clearly desirable to have control units capable of driving components with different timing requirements, thereby obtaining much greater flexibility and interchangeability of system components.
The overall system timing requirements include the following limitations. First, a pulse train of the desired frequency must begin with a full-width pulse. Secondly, each of the pulse trains must also end with a full-width pulse. Thirdly, the delay or gap between pulse trains of different frequencies must be greater than or equal to the slowest (or widest) pulse width spacing. Meeting these system requirements is essential for coordination with the master system clock while operating asynchronously to it. Meeting these specifications and simultaneously selectively choosing between a variety of pulse trains with different frequencies poses a compounded problem. Prior art methods of producing a plurality of clock pulses with different frequencies includes providing a plurality of freerunning drive clocks. However, the different frequencies of these free-running clocks necessarily implies a continually changing phase relationship between the pulse trains which makes the task of meeting the system requirement much more complex.